Exascale computing is an emerging computing technology that will require the integration and packaging of high performance and low-power multi-core processors and high-bandwidth memory. Conventional techniques for scaling semiconductor devices are becoming increasingly problematic with regard to gate leakage currents and interconnect wiring delays, and are not suitable for exascale computing. Currently, three-dimensional (3D) chip stacking techniques using micro-bump and through-silicon-via (TSV) technologies are being utilized to reduce interconnect lengths and reduce the parasitic capacitance of wiring, which dramatically increases chip performance as compared to traditional 2D IC (integrated circuit) packaging designs.
With conventional solder bump bonding techniques, chip stack yields are improved by removing oxidation (oxide film) from the solder bumps and metallic bonding surfaces using a liquid flux. A flux is a chemical agent that dissolves oxide films on the metal surface of bonding interconnections. This approach requires removing the flux residue after the bonding process to avoid reliability problems. However, as chip sizes increase, and as micro-bump pitch is decreased to achieve higher bandwidth I/Os for 3D applications, the removal of flux residue becomes more difficult.
Fluxless bonding techniques have been proposed. For example, a conventional fluxless bonding method involves flip chip bonding in a reducing atmosphere such as formic acid vapor to dissolve oxide films on solder bumps and metallic bonding surfaces. With this process, however, the use of formic acid raises issues of safety. In addition, the use of formic acid vapor requires additional process steps and time to evacuate all of the reducing gas from the bonding environment for each bonding process. Other fluxless bonding techniques involve pre-applying underfill material with a non-conductive paste (NCP) or a non-conductive film (NCF). NCP and NCF contain flux agent, so they do not need separate flux applying and flux residue cleaning processes. NCP and NCF techniques may not be suitable for bonding large dies with a large number of micro bumps. Indeed, with NCP and NCF techniques, the fillers are sometimes trapped in the bonding interface, and the process requires a high bonding force to eliminate material entrapment between corresponding solder bumps and bonding pads. In addition, depending on the underfill material that is used, NCP and NCF techniques make it difficult to find alignment marks that are utilized by bonding systems for alignment.